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PRELIMINARY
CY24206
MediaClockTM DTV, STB Clock Generator
Features * Integrated phase-locked loop * Low-jitter, high-accuracy outputs * 3.3V operation Benefits Internal PLL with up to 400-MHz internal operation Meets critical timing requirements in complex system designs Enables application compatibility
Part Number CY24206-1
Outputs 3
Input Frequency 27 MHz
Output Frequency Range 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)
CY24206-2
4
27 MHz
CY24206-3
4
27 MHz
CY24206-4
4
27 MHz
Logic Block Diagram
XIN XOUT P OSC. Q VCO OUTPUT MULTIPLEXER AND DIVIDERS CLK1 CLK2 REFCLK FS0 FS1 FS2 OE CLK3 (-2, -3,-4)
PLL
Pin Configurations CY24206-1 16-pin TSSOP
XIN VDD AVDD OE AVSS VSSL CLK1 CLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FS2 FS1 VSS N/C VDDL
VDDL
VDD
AVDD
AVSS
VSS
VSSL
CY24206-2,3,4 16-pin TSSOP
XOUT XIN VDD AVDD OE AVSS VSSL CLK1 CLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT FS2 FS1 VSS CLK3 VDDL FS0 REFCLK
FS0 REFCLK
Cypress Semiconductor Corporation Document #: 38-07451 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 27, 2003
PRELIMINARY
Frequency Select Options
FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CLK1 (-1,-2) 81 81.081 74.175 74.250 81 81.081 74.175 74.250 CLK1 (-3,-4) 81 81.081 74.17582 74.25 81 81.081 74.1758 74.25 CLK2 27 (CLK1/3) 27.027 (CLK1/3) 24.725 (CLK1/3) 24.75 (CLK1/3) 27 27 27 27 CLK3 (-2, -3,-4) 27 (CLK1/3) 27.027 (CLK1/3) 74.17582 (CLK1) 74.25 (CLK1) 27 (CLK1/3) 27.027 (CLK1/3) 74.175 (CLK1) 74.25 (CLK1)
CY24206
REFCLK 27 27 27 27 27 27 27 27
Units MHz MHz MHz MHz MHz MHz MHz MHz
Pin Description
Name XIN VDD AVDD OE AVSS VSSL CLK1 (-1,-2) CLK1 (-3,-4) CLK2 REFCLK FS0 VDDL N/C (-1) CLK3 (-2,-3,-4) VSS FS1 FS2 XOUT Pin Number 1 2 3 4 5 6 7 7 8 9 10 11 12 12 13 14 15 16 Description Reference Crystal Input. Voltage Supply. Analog Voltage Supply. Output Enable, weak internal pull-up. 0 = outputs off, 1 = outputs on. Analog Ground. VDDL Ground. 81-/81.081-/74.175-/74.250-MHz Clock Output (frequency selectable). 81-/81.081-/74.17582-/74.25-MHz Clock Output (frequency selectable). 27-/27.027-/24.725-/24.75-MHz Clock Output (frequency selectable). Reference Clock Output. Frequency Select 0, weak internal pull-up. Voltage Supply. No Connect. 27-/27.027-/74.175-/74.25-MHz Clock Output (frequency selectable). Ground. Frequency Select 1, weak internal pull-up. Frequency Select 2, weak internal pull-up. Reference Crystal Output.
Absolute Maximum Conditions
Parameter VDD VDDL TJ Description Supply Voltage I/O Supply Voltage Junction Temperature Digital Inputs Electro-Static Discharge AVSS - 0.3 2 Min. -0.5 Max. 7.0 7.0 125 AVDD + 0.3 Unit V V C V kV
Recommended Operating Conditions
Parameter VDD/AVDDL/VDDL TA CLOAD fREF Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency 27 Min. 3.135 0 Typ. 3.3 Max. 3.465 70 15 Unit V C pF MHz
Document #: 38-07451 Rev. *A
Page 2 of 5
PRELIMINARY
DC Electrical Specifications
Parameter[1] IOH IOL IIH IIL VIH VIL IVDD IVDDL RUP Name Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Pull-up resistor on Inputs Description VOH = VDD - 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VIH = VDD VIL = 0V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current VDD = 3.14 to 3.47V, measured VIN = 0V 100 Min. 12 12 - - 0.7 Typ. 24 24 5 -
CY24206
Max.
Unit mA mA
10 50 0.3 25 20 150
A A VDD VDD mA mA k
AC Electrical Specifications
Parameter[1] DC ER EF t9 t10 Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. CLK1, CLK2 Peak-Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 200 3 Max. 55 Unit % V/ns V/ns ps ms
Test and Measurement Set-up VDDs 0.1 F DUT Outputs CLOAD
GND Voltage and Timing Definitions
t1 t2 VDD 50% of VDD Clock Output 0V
Figure 1. Duty Cycle Definitions
Note: 1. Not 100% tested.
Document #: 38-07451 Rev. *A
Page 3 of 5
PRELIMINARY
CY24206
t3
t4 V
DD
80% of V DD 20% of VDD 0V
Clock Output
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
Ordering Information
Ordering Code CY24206ZC-1 CY24206ZC-1T CY24206ZC-2 CY24206ZC-2T CY24206ZC-3 CY24206ZC-3T CY24206ZC-4 CY24206ZC-4T Package Name Z16 Z16 Z16 Z16 Z16 Z16 Z16 Z16 Package Type 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP Operating Range Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
16-Pin TSSOP - Tape and Reel Commercial 16-Pin TSSOP - Tape and Reel Commercial 16-Pin TSSOP - Tape and Reel Commercial 16-Pin TSSOP - Tape and Reel Commercial
Package Drawing and Dimensions
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07451 Rev. *A Page 4 of 5
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
Document History Page
Document Title: CY24206 MediaClockTM DTV, STB Clock Generator Document Number: 38-07451 REV. ** *A ECN NO. 120901 123046 Issue Date 12/10/02 03/03/03 Orig. of Change CKN CKN New Data Sheet Added -4 to data sheet Description of Change
CY24206
Document #: 38-07451 Rev. *A
Page 5 of 5

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